EEPROM (electrically erasable and programmable read only memory) is widely used as one of electrically erasable and programmable non-volatile semiconductor memory devices. These memory devices (memories), typified by flash memory which is currently widely used, have a conductive floating gate surrounded by an oxide film or a trap insulating film under a gate electrode of a MISFET, and a charge storage state in the floating gate or trap insulating film is taken as memory information of the memories and the charge storage state is read as a threshold voltage of the transistor. The trap insulating film means an insulating film capable of storing (accumulating) charges, and a silicon nitride film is an example. A threshold voltage of a MISFET is shifted by injection/release of charges to/from such a charge storage region to operate the MISFET as a memory element. As the flash memory, there is a split-gate-type cell using MONOS (metal-oxide-nitride-oxide semiconductor). By using a silicon nitride film as a charge storage region, this MONOS flash memory has better reliability of data retention than a conductive floating gate film as the silicon nitride film discretely stores charges, and oxide films over and under the silicon nitride film can be thinned as the silicon nitride film has good reliability, and thus there are advantages such that a voltage lowering in reading and programming operations can be attained, etc.
For example, Japanese Patent Application Laid-Open Publication No. 2003-309193 (Patent Document 1) discloses a non-volatile memory cell transistor including a first gate electrode (control gate electrode) and a second gate electrode (memory gate electrode) disposed via an insulating film and a charge storage film, wherein the structure is processed so that a height of the first gate electrode from a surface of a substrate is lower than a height of the second gate electrode film from the substrate surface or a height of a gate electrode of a transistor formed in a peripheral circuit from the surface of the substrate.
Japanese Patent Application Laid-Open Publication No. 2006-054292 (Patent Document 2) discloses a method of arranging isolated subsidiary patterns being adjacent to a select gate electrode in a memory cell that has a split-gate structure and forming contacts to wiring portions formed in a self-aligned manner by filling polysilicon of a sidewall gate to a gap between the subsidiary patterns.
Japanese Patent Application Laid-Open Publication No. 2006-049737 (Patent Document 3) discloses a memory cell in which a memory gate line is formed on a sidewall of a select gate line via an insulating film, a contact portion extended in an X direction is provided from above a second portion of the select gate line to a device isolation region, and the memory cell is connected to wirings via plugs buried in contact holes formed on contact portions.
Japanese Patent Application Laid-Open Publication No. 2005-347679 (Patent Document 4) discloses a MONOS (metal oxide nitride oxide semiconductor) type non-volatile memory cell in which a cap insulating film to be a mask during a processing of a select gate electrode is formed on the select gate electrode, and a memory gate electrode is formed on a sidewall of a stacked film formed of the select gate electrode and the cap insulating film.